Routers, switches, and line cards need higher bandwidth, higher port density, and up to 800 Gigabit Ethernet (GbE) connectivity to handle the growing traffic in data centers driven by 5G, cloud services, and artificial intelligence (AI) and machine learning applications. “The industry is adopting a 112G PAM4 ecosystem for high-density switching, packet processing, and optical connections,” said Bob Wheeler, chief network analyst at The Linley Group. “Microchip’s META-DX2L solution is optimized to meet these requirements, connecting line cards to switching elements and optical equipment at various speeds for 100GbE, 400GbE, and 800GbE connectivity.”
With its 1.6T bandwidth, high density, and small size, the META-DX2L Ethernet PHY, powered by 112G PAM4 SerDes technology and capable of achieving Ethernet speeds from 1 to 800 GbE, is an industrial-grade device offering versatile connectivity for maximum design reuse in applications ranging from a timer, multiplexer/demultiplexer, or inverse demultiplexer to a 2:1 multiplexer (mux). The interconnect and multiplexing/demultiplexing functions are highly configurable, maximizing the switching device's I/O bandwidth to provide the flexible connections required for multi-speed cards compatible with a wide variety of optical connections. PHY's low-power PAM4 SerDes enables you to provide next-generation interface speed for cloud data centers, computing clusters for AI and machine learning, 5G and infrastructure to telecom service providers, whether it's long-distance direct attach copper (DAC) cables, backplanes, or connections to optical devices.
“For the 56G generation, we introduced the market’s first terabit PHY, the META-DX1, followed by an equally transformative 112G solution that delivers the capabilities systems developers need to address the new challenges posed by cloud data centers, 5G networks, AI, and machine learning,” said Babak Samimi, vice president of Microchip’s communications business unit. “With its ability to achieve up to 1.6T of bandwidth in a low-power architecture with the smallest possible footprint, the META-DX2L PHY doubles the bandwidth of previous solutions on the market and sets a new standard for efficiency.”
META-DX2L comes in the smallest package on the market, 23 x 30 mm, saving the space needed to achieve the line card densities required by hyperscalers and system developers. Here are some of the product's key features:
- GbE PHY with 2x 800 GbE, 4x 400 GbE and 16x 100/50/25/10/1
- It supports Ethernet, OTN, and Fibre Channel data transmission speeds.
- It supports proprietary data rates for AI and machine learning.
- Integrated 2:1 multiplexer enabling high availability/
protection - Highly configurable interconnection for multi-speed services on any port
- Constant latency that allows IEEE 1588 Class C/D PTP at any system level
- FEC termination, monitoring, and conversion between various interface speeds
- 112G PAM4 SerDes 32 LR (long-reach) programmable to optimize consumption with respect to performance
- Compatible with DAC cables, including auto-negotiation and link formation
- Industrial temperature range for outdoor applications
- Complete Software Development Kit (SDK) with easy upgrade, hot-reboot capabilities, and compatibility with the proven META-DX SDK
- Microchip supplies a full range of proprietary products, reference designs, and evaluation boards to enable customers to build systems based on META-DX2L devices. In addition to its Ethernet PHY technology, Microchip also provides a complete system solution to system vendors, consisting of PolarFire® FPGAs,the high-performance ZL30632 PLL, oscillators, voltage regulators, and other components pre-validated as a system with META-DX2L to expedite production of designs.
Product availability
Samples of the first META-DX2L devices are expected during the fourth quarter of 2021. For more information, please visit the PM6200 META-DX2Lor contact a Microchip sales representative.
