From cloud computing to autonomous vehicles, the demand for faster memory interfaces is accelerating. A disruptive technological feature of fast interfaces like DDR5, LPDDR5, and GDDR6 is equalization at the memory chip receivers, which recovers signals degraded along their path through the printed circuit board (PCB). Hardware engineers need to minimize the risk of signal integrity issues in memory bus designs, which requires the ability to predict signal quality after equalization, prototype the design, and test its performance.

Keysight's PathWave ADS 2022, a workflow for designing and testing next-generation memory, enables hardware engineers to meet their time-to-market requirements and deliver a reliable, high-performance end product. The Memory Designer in PathWave ADS 2022 faces the following design challenges:

  • Accurate modeling of transmitter and receiver behavior by generating advanced simulation models for both DDR transmitters and receivers, with flexible equalization and external clock inputs.
  • Optimizing equalization settings to predict design margins with an advanced simulator that uses adaptive equalization to find the optimal settings for the best signal integrity in the data link.
  • Quantifying the margin in the eye diagram mask by predicting how much the eye will close at different standard-specific bit error rates (BER), and reporting the remaining margin.
  • Finding failure conditions using design exploration by generating a batch of simulation lists to sweep through all possible design parameters and reporting pass/fail configurations in a spreadsheet.
  • Confidence in design completion, from inception to testing, by performing automated compliance reporting on simulated waveforms and using consistent measurement science to identify problems early and efficiently test potential solutions.

“The cutting-edge PathWave ADS signal integrity simulator helps Xilinx in our development of advanced memory systems. Working with Keysight allows us to optimize system memory solutions for our customers,” said Thomas To, Director of System Memory SI at Xilinx.

“DDR5 is a revolutionary technology that requires designers to re-evaluate their simulation and measurement strategy,” said Brig Asay, Director of Strategic Planning in the Internet Infrastructure Group at Keysight. “Keysight’s expertise in DDR5, both in simulation and measurement techniques, allows us to help our clients navigate the challenges of this technology and guide them to success in their designs on the first iteration.”

Additional information about PathWave ADS Memory Designer can be found at: