A Simulink model based on the system specifications helped engineers quickly evaluate design ideas and improve collaboration between engineering teams. Simulink and Simulink HDL Coder enabled engineers to create prototypes in just a few weeks and eliminate the need for manual code generation. By using EDA Simulator Link, Semtech engineers reused the Simulink system model to test various critical design points, verify the VHDL in less than a day, and reduce the overall verification time from weeks to days.
“We faced the challenge of accelerating the development time of a digital receiver and finding ways to improve the development workflow. MathWorks tools allowed us to explore new alternatives and features, ultimately leading to an optimized design with better performance,” says Frantz Prianon, CI Design Engineer at Semtech. “With Simulink and Simulink HDL Coder, once the model is simulated, we can generate the VHDL directly, prototype it on an FPGA, and thoroughly verify the VHDL implementation. This saves a significant amount of time, and the generated code includes optimizations we hadn't even considered.”.
“Semtech represents the vanguard of semiconductor companies adopting new methodologies to generate highly integrated mixed-signal devices. With Simulink and model-based design, Semtech was able to evaluate various design ideas at the prototyping stage, as well as eliminate bottlenecks in their workflows,” says Ken Karnofsky, senior strategist for signal processing applications at MathWorks. “Furthermore, the automatic generation of HDL code with Simulink HDL Coder enabled Semtech to eliminate coding errors and quickly create a working FPGA prototype.”.
Signal Processing Toolbox, DSP System Toolbox, Fixed-Point Toolbox, and Simulink Fixed-Point all contributed to accelerating the development of the digital receiver. Model-based design has enabled Semtech to transition to a fully digital platform, advance digital and mixed-signal designs, and reduce power consumption while supporting the integration of the design workflow with other products such as Mentor Graphics and Questa Advanced Simulator. Semtech is currently working on an ASIC implementation of the receiver.
Agilent Technologies introduces automation software for network operators' Inter-RAT LTE-CDMA compliance testing plans
Agilent Technologies Inc. has optimized its CDMA N5971A Interactive Functional Testing (IFT) software by integrating the automation from IFT N5973A for the Inter-RAT LTE-CDMA conformance test plan. This solution enables developers and operators to quickly generate...
