To double the Nyquist bandwidth of an ADC receiver, a traditional time-interleaving method is often used. However, alternative architectures offer more advantages. In this three-part series, we describe the options for first-time direct Nyquist sampling of a bandwidth from 2 GHz to 18 GHz using commercially available ADCs. Part 1 presents the challenges and possible approaches. Part 2 describes quadrature direct sampling in detail, along with measured results. Part 3 compares the quadrature results with time-interleaving, enabling users to select the optimal option based on their system objectives.

Part 1: Applications, Interleaving Basics, and Options of the AD9084

The Aliasing Problem
: Figure 1a shows an analog spectrum with a desired yellow signal in Nyquist zone 1 (0 - fS/2) and a blocking blue signal in Nyquist zone 2 (fS/2 - fS). According to the sampling theorem, digitally sampled analog signals will appear at integer multiples of fS. As shown in Figure 1b, both the narrowband blocking signal and the desired signal are copied at positive and negative integer multiples of fS. The architectural challenge for the ADC is how the systems engineer can mitigate this known problem using alternative sampling methods.

Figure 1. Spectral view: (a) Analog domain spectrum showing two frequency-spaced signals; (b) sampled spectrum of a 40 GSPS ADC; in this case, the two analog domain signals can be resolved into a single Nyquist band; (c) sampled spectrum of interleaved ADCs, each at 20 GSPS. Note that the amplitude spectra overlap, preventing resolution of the two signals. This article shows that the phase information between interleaved slices is different and allows for multiple options for ADC interleaving, including both quadrature and time interleaving.
The Nyquist theorem states that unwanted aliasing effects occur when the signal bandwidth is greater than fS/2. In sampled systems, the single spectrum will only be visible from 0 to fS/2. Higher-order Nyquist signals will alias or refold in the Nyquist region (0 to fS/2), as shown in Figure 1c, in the form of unwanted images. Image signals generated from frequencies above fS/2 will block the desired signals, reducing the SFDR and sometimes rendering a signal unrecoverable.

In traditional EW and COMINT systems, where blockers are present in higher-order Nyquist regions, antialiasing (AA) filters are used. In the first Nyquist sampling, low-pass filters are used to reject blockers above fS/2 and prevent their images from being re-encoded in the first Nyquist. These systems work well if the desired signal is always in the first Nyquist region. However, this will be directly dictated by the sampling frequency.

This configuration is ineffective when the interfering signal is just above half the sampling frequency (fS/2) and the target signal is just below fS/2. In Figure 2, the interfering signal is too close to apply an AA filter without risking the loss of some of the desired bandwidth. A best practice is to use a 20% frequency guard band around fS/2.
A popular alternative to Nyquist first sampling is undersampling, which places the bandwidth of the desired signal in a higher Nyquist ADC region. In this case, the desired signal is in a higher-order band than fS/2. The AA filter would essentially be a bandpass filter (BPF) surrounding the desired signal in the higher-order band. This BPF rejects frequencies outside the passband, which could be a blocker or out-of-band noise.

Interleaving
: Full-Rate Offload.
Traditional time interleaving of two or more ADCs with delayed timers has both an advantage and a disadvantage. When two cores are used to simultaneously sample a signal with a sampling frequency of fS, the resulting sampling frequency is simply 2 × fS. The ADCs must have a fixed clock phase relationship for interleaving to function correctly. The clock phase relationship is governed by Equation 1, where n is the specific ADC and m is the total number of ADCs.

For a dual ADC interleaving ratio, the sampling clocks of each channel must be 180° out of phase or sampled alternately at the positive and negative edges of a clock with an ideal 50% duty cycle. These timing specifications can be difficult to meet using external timing solutions without introducing new interleaving devices. Furthermore, the front-end RF divider would need ideal characteristics for amplitude and phase matching; otherwise, unwanted spurious frequency power may be introduced at the cutoff sampling rate fS/2.
Depending on how the back-end digital processing is used, a full-speed bitstream may not be desirable unless the full interleaved Nyquist bandwidth fS/2 can be used for the signals of interest. Some interleaving architectures may limit the dynamic range to 8 bits of a higher-resolution converter.
In this case, there would be no back-end digital corrections for small variations in the ADC channels, such as offset, gain, and phase delay. Therefore, these mismatches would appear as interlacing artifacts within the Nyquist frequency spectrum. They would decrease the usable dynamic range of the interlaced converter channel with unwanted imaging. With the Analog Devices AD9084 Apollo MxFE™, there are two options that take advantage of full frequency offloading. Figure 3 shows a single pair of 12-bit interlaced ADCs, while Figure 4 shows two pairs of interlaced ADCs. To achieve the two-channel outputs, the bit resolution is reduced to 8 bits per sample.

 

Overview of Direct Quadrature Sampling:
Direct quadrature sampling is an alternative form of interleaving. The more common ping-pong interleaving method involves sequentially synchronizing two neighboring ADCs. This is typically done by doubling the clock frequency or by sampling at both the rising and falling edges of the input clock. Quadrature interleaving does not invert the clock phase but synchronizes two ADCs simultaneously with a common in-phase clock. A 90° phase shift of the RF input provides the information needed to resolve multiple Nyquist zones and double the effective sampling rate. This offers the advantage that post-ADC processing does not need to double the sampling rate.
In practice, the 90° phase shift is achieved with a hybrid coupler, often called a hybrid splitter. Currently, wideband hybrid couplers exist that cover a broad bandwidth from 2 GHz to 18 GHz. However, a well-known problem in quadrature sampling is that any phase or amplitude mismatch in the I/Q balance creates unwanted perceived energy at the image frequency. The effect of this mismatch is unbalanced, as the differences between the two signals are magnified the larger the imbalances. This creates spurious primary image interlacing at fS ± fIN due to the gain and phase mismatch between the I and Q signals.
Commercial hybrid couplers have historically only supported narrow bandwidths for smaller frequency targets. Wideband performance specifications are still maturing. With the introduction of 2 GHz to 18 GHz wideband hybrid couplers, matching performance is moderate, as it is feasible to achieve a minimum of a few dB of amplitude error matching and varying degrees of phase error matching across their bandwidth. The spurious power of practical interlacing using only hardware quadrature is -20 dBc at best. This is simply an unacceptable technical solution for most modern applications. Therefore, relying solely on a hardware solution for this type of interlacing will not suffice. A back-end quadrature error correction (QEC) matching algorithm will be required in the digital processing to achieve SFDR performance of -50 dBc or better across a wide bandwidth.

Interleaving Options with the AD9084 DSP
The AD9084 is a 4T4R RF sampling converter with an RF input bandwidth of 18 GHz. Figure 5 shows the ADCs and the integrated DSP for half of the ADCs integrated into the IC. To avoid the need for full-speed data offloading, interleaving options were developed for both time interleaving and quadrature interleaving that maintain the use of the integrated DSP. This allows monitoring a full bandwidth of 2 GHz to 18 GHz while still decimating at a lower rate to reduce the digital payload and power on adjacent digital chips.

Direct Quadrature Sampling: PFILT QEC.
Quadrature interlacing uses two ADC cores, splitting the RF input signal in hardware into 0° and 90° phases. The separate signal processing is performed as if the two signals were in ideal perfect quadrature. Unfortunately, the two split signals are not ideal due to significant mismatches in both phase and amplitude, which are common in the hybrid performance of current hardware. However, a back-end quadrature error correction algorithm can compensate for both the amplitude and phase mismatch between the two signals.
After using a training signal to establish correction coefficients across the entire bandwidth (BW) of interest, the image spur of the quadrature sampling architecture can be mitigated to more than -50 dBc using digital filter processing techniques. This maintains a consistent SFDR without the undesirable 8× sub-ADC time interlacing artifacts found in many high-speed architectures.

Direct Quadrature Sampling: CFIR QEC.
A variation of the quadrature interleaving principle allows filtering of the digital signal before the QEC correction block in complex FIR (CFIR). SFDR performance in this case is usually improved, as the lower-frequency ripple mismatch between the two channels can be more easily corrected with a longer processing latency. The numerically controlled oscillator (NCO) frequencies between the two DDCs are not set to be equal; instead, NCO2 = fS - NCO1. The reason for this NCO frequency difference is detailed in Part 2 of this series of articles. The 32-bit digital resolution accuracy of each NCO tuning word ensures that there is no residual frequency mismatch between the DDCs that would contribute to unwanted spurious performance. A subsequent summing step merges the two channels into one by canceling the first or second Nyquist.

Time Interleaving with PFILT or CFIR Error Correction
The same interleaving principles mentioned for quadrature can also be applied to traditional time interleaving methods using internal inverted sampling timers. Instead of using a front-end quadrature hybrid, a real divider would be used for multi-channel time interleaving with post-error correction. Each signal would be corrected with digital filtering coefficients. After filtering, two decimated data channels would be generated, which would then need to be reassembled using digital signal processing techniques.

 

Two time-interleaving options were evaluated using the integrated DSP. Figure 8 shows time-interleaving with PFILT correction, and Figure 9 shows the time-interleaving configuration with CFIR correction.

Additional Considerations Regarding Interleaving:
Mismatch.
Interleaving multiple ADCs presents challenges, including the appearance of spurious frequency power (spurious signals) in the output spectrum due to non-ideal imperfections in each ADC core. These imperfections arise primarily from mismatches between the interleaved ADCs, especially in gain and phase or timing.
Small manufacturing variations, even for two adjacent ADCs on the same silicon die, can cause enough gain variation to introduce a spurious gain mismatch. In the case of gain mismatch, there is no viable way to measure the gain mismatch unless a signal is presented to both ADCs for measurement. The gain mismatch will result in a spurious signal in the output spectrum related to the input frequency and the sampling frequency. The spurious signal will appear in fS - fIN.
To minimize the spurious signal caused by the gain mismatch, a correction strategy is employed. The gain of one of the ADCs is chosen as the reference, and the gain of the other ADC is adjusted to match that gain value as closely as possible. The closer the gain values ​​of each ADC are matched to each other, the smaller the resulting spurious signal will be in the output spectrum.

Heavy Interlacing:
Some commercial architectures employ extensive sequential interlacing, using 8× or more ADC cuts to expand the Nyquist bandwidth. For example, 8-way interlacing would create interlacing spurious frequencies at fS/8, fS/4, 3fS/8, etc. This would create a non-normal noise spectral density (NSD) distribution with interlacing spurious frequencies around all eight ADC cuts. Without proper calibration to suppress these spurious frequencies, a sophisticated table or spurious calculation tool for navigating the interlacing artifacts quickly becomes unmanageable.

Conclusion
In the first part of this series of articles, we presented a new method for direct sampling from 2 GHz to 18 GHz. From electronic warfare to communications intelligence, there are numerous cases where continuous monitoring from 2 GHz to 18 GHz is required. Without the need for dedicated AA filters, systems can resolve signals from multiple Nyquist zones. With careful time quadrature error correction techniques or adjacent quadrature interleaved ADCs, systems can effectively double the sampling rate of a given digitizer. By utilizing the enhanced DSP functionality of the Apollo MxFE device, FPGA resources can be minimized while still monitoring a full spectrum from 2 GHz to 18 GHz, all within a single Nyquist.
Six options have been introduced with detailed descriptions in Part 2 and Part 3.
► Full frequency offload, ADCs sandwiched on opposite sides
► Full frequency offload, adjacent ADCs sandwiched
► Direct quadrature sampling: error correction with PFILT
► Direct quadrature sampling: error correction with CFIR
► Time interlacing: error correction with PFILT
► Time interlacing: error correction with CFIR

References
1Gabriele Manganaro. «Advanced Data Converters». Cambridge University Press, 2012.
Kester, Walt. «Analog-Digital Conversion». Analog Devices, Inc., 2004. Ali, Ahmed. High Speed ​​Data Converters. IET, 2016.

Harris, Jonathan. «The ABCs of Interleaving ADCs». Analog Devices, Inc., 2019.
Manganaro, Gabriele and Robertson, David. "Interleaving ADCs: Unraveling the Mysteries." Analog Dialogue, Vol. 49, July 2015.

Authors: Ian Beavers, field applications engineer, Peter Delos, senior principal engineer, Brian Reggiannini, senior principal engineer, and Connor Bryant, systems applications engineer at Analog Devices

About the authors

Ian Beavers is a field applications engineer and customer lab manager for the Aerospace and Defense Systems team at Analog Devices in Durham, North Carolina. He has been with the company since 1999. Ian has over 25 years of experience in the semiconductor industry. He earned a bachelor's degree in electrical engineering from North Carolina State University and an MBA from the University of North Carolina at Greensboro.
Peter Delos is the technical lead for the Aerospace and Defense Group at Analog Devices in Greensboro, North Carolina. He earned his bachelor's degree in electrical engineering from Virginia Tech in 1990 and his MBA from NJIT in 2004. Peter has over 30 years of experience in the industry. He has spent most of his career designing advanced analog/RF systems at the architecture, printed circuit board, and integrated circuit levels. Currently, he focuses on miniaturizing receiver designs, waveform generators, and high-performance synthesizers for phased-array applications.
Brian Reggiannini is a senior principal systems design engineer. He has designed, implemented, and supported system-level calibrations for several generations of Analog Devices wireless transceiver products. His technical interests include signal processing, machine learning, embedded systems, and systems involving digitally assisted analog components. Brian earned his Sc.B., Sc.M., and Ph.D. degrees from Brown University in 2007, 2009, and 2012, respectively.
Connor Bryant is a systems applications engineer at Analog Devices and works in the Aerospace and Defense Business Unit in Durham, North Carolina. He joined ADI in 2023. He currently focuses on the design and analysis of RF mixed-signal chains. He obtained his Bachelor of Science in Electrical Engineering from North Carolina State University in 2022 and his Master of Science in Electrical Engineering from North Carolina State University in 2023.