Quadrature interlacing offers a novel solution for extending sampling bandwidth without the complexities of managing double-frequency clocks, clock inversion, or doubling the data output.

Introduction
: Part 1 describes the objectives of interlacing, discusses the errors that create interlacing artifacts, and introduces the range of 40 GSPS analog-to-digital converter (ADC) options that utilize the AD9084. Part 2 explores the quadrature sampling option, along with a quadrature correction mechanism, in detail.
An emerging capability that is enhancing data conversion products is the significant inclusion of embedded digital signal processor (DSP) cores. A relevant example of the integrated DSP in modern ADCs is doubling the effective sampling rate without increasing back-end digital data rates. Using two quadrature input ADCs and a quadrature correction algorithm, a dual 40 GSPS ADC can be configured to produce four 4 GHz downconverting digital outputs, monitoring a bandwidth from 2 GHz to 18 GHz, within a single multichannel converter IC.
First, direct quadrature sampling is described in relation to the most common zero IF (ZIF) architectures. Quadrature errors are identified, along with a description of the embedded digital processing required for quadrature error correction (QEC). Analog RF front-end components, ADC data sampling, embedded DSP processing, and final processing of the data converter's I/Q outputs are then discussed. The measured results show amplitude and phase errors both before and after Quadrature Error Correction (QEC), and the final measured image rejection demonstrates effective direct quadrature sampling from 2 GHz to 18 GHz. The approach is described for the AD9084 IC, but it is generally applicable to any wideband sampling system.

Figure 1: Quadrature sampling principles compared to a ZIF architecture.

Principles of Quadrature Sampling.
Figure 1 shows a traditional ZIF architecture. The architecture creates two quadrature IF signals (90° out of phase) through a quadrature RF downconverting mixer. In this case, quadrature is created in the local oscillator circuitry from two physically separate mixer and LO sets, each with a 90° phase shift. The result is two quadrature IF frequencies. The ability to resolve whether the RF is above or below the LO frequency is visualized by a phase inversion between the I and Q signals at the LO frequency, as shown in Figure 1. Digital downconverters (DDCs) that process data streams from real data converters and create an I/Q output data stream in a narrow bandwidth centered by a numerically controlled oscillator (NCO) are also driven by these same principles.
Figure 1. Principles of quadrature sampling compared to a ZIF architecture.

The principles in Figure 1 allow for the description of direct quadrature sampling. If the 90° phase shift is adjusted so that two parallel ADCs simultaneously sample the same quadrature RF input, a phase inversion of the I/Q signals occurs at the Nyquist limit during the sampling process. This property can be exploited to effectively double the ADC's sampling frequency, as shown in Figure 2.
In practice, the 90° phase shift is achieved with a hybrid coupler, also marketed as a hybrid splitter. Wideband hybrid couplers are currently available that cover bandwidths from 2 GHz to 18 GHz.

Quadrature Errors:
A well-known problem in quadrature sampling is that any phase or amplitude mismatch in the I/Q balance creates unwanted perceived energy at the image frequency. This problem also applies to the direct quadrature sampling approach and must be addressed with a back-end algorithm.
The operational concern is shown in Figure 2. The concern is that an unwanted signal in the image band can backtrack into the signal band. The image level is a function of the amplitude and phase mismatch of the ideal quadrature and creates the need for a QEC method.
Figure 2. Direct Quadrature Sampling Image: The concern in direct quadrature sampling is that an unwanted signal in the image band can backtrack into the signal band. The image level is a function of the amplitude and phase mismatch of the ideal quadrature and is seen in the blocking image level compared to the blocking level. The blocking image is further reduced with a QEC method.
Image rejection levels can be calculated as follows:
IRR = Image rejection ratio (dB) P = 10(IRR/10)
A = Amplitude mismatch
θ = Phase error

For a given IRR and amplitude error

For a given IRR and phase error

Figure 2: Direct Quadrature Sampling Image: The concern with direct quadrature sampling is that an unwanted signal in the image band can be folded into the signal band. The image level is a function of the amplitude and phase mismatch of the ideal quadrature and is seen in the blocking image level compared to the blocking level. The blocking image is further reduced using a QEC method.

Figure 3. Amplitude and phase errors between channels I and Q to achieve specific image rejection values. Axes are shown on a logarithmic scale.

Figure 3 shows the magnitude of image rejection versus the required amplitude and phase error. For example, an image rejection magnitude of 60 dBc requires a phase accuracy of less than one-tenth of a degree and an amplitude match of hundredths of a dB. This level of image rejection is impractical in hardware alone using the accuracy of currently available commercial RF components. Therefore, to use the direct quadrature sampling approach, additional digital error correction is needed. The configurations used for QEC will be described in the following sections.

Figure 4. The AD9084 direct quadrature sampling configuration using the PFILT in a semi-complex finite impulse response (FIR) filter mode for QEC.

Quadrature Sampling with Programmable Filter (PFILT) QEC.
Figure 4 shows a block diagram of the AD9084 configuration for direct quadrature sampling with PFILT QEC. For the measured FFTs shown, the input frequency was set to 7.1 GHz, the NCO on channel 1 was set to 7 GHz, and the input signal appeared in the baseband data at 100 MHz. The image frequency is reflected around fs/2 and appears at 12.9 GHz. The NCO of channel 2 was set to 13 GHz to monitor the image frequency appearing in the baseband output at -100 MHz.
The sequence of steps for the test data in the following figures is:
A functional check is performed, then the background ADC calibrations are frozen to prevent crosstalk between channels due to new ADC calibrations. The frequency was then swept in 25 MHz steps across a 4 GHz bandwidth. For each data capture, the NCO1 frequency was set to Fin - 100 MHz, and for the second NCO, NCO2, the frequency was set to 20 GHz - the NCO1 frequency. This resulted in both NCO frequencies reflecting the sampling frequency divided by two, fs/2.
From the measured data of Ch1 and Ch2, quadrature correction coefficients were calculated and applied to the embedded FIR, as shown in Figure 5. Additional data were then acquired, and the performance after QEC was evaluated. This sequence was repeated four times to cover the entire operating range from 2 GHz to 18 GHz.
The resulting 4 GHz bandwidth corrections are shown below. The AD9084 has four banks of filter coefficients that can be quickly selected. This programmable feature allows optimization of the coefficients used based on the input frequency of interest, given the programmed NCO frequency.
The suitability of the semi-complex PFILT structure can be illustrated with a simple example. The direct quadrature sampling configuration involves dividing the signal into separate I and Q paths, each of which is sampled by an individual ADC.

Figure 5. Quadrature sampling mode.

QEC is a relative form of equalization. For example, path I can be considered ideal, and path Q can be considered to coincide with path I. Therefore, the response of path Q can be modeled as the combination of (a) a nominal phase shift of 90°, (b) the common response of path I, and (c) a mismatch or delta response of path Q relative to path I, as shown in Figure 6.

Figure 6. Relative quadrature sampling model in terms of nominal 90° phase shift H 90 (ω) and mismatch response H Δ (ω).

Figure 7 shows the result of stimulating this relative quadrature sampling model with a sinusoidal input x(t) = cos(ω0). The nominal phase shift of 90° converts a cosine to a sine, and the delta response H(Δ)(ω) = A(Δ)(ω)e((jθΔ(ω)) modifies the amplitude and phase of the result.

Figure 7. Stimulating the quadrature sampling model with a cosine input results in a sine input to the second ADC along with amplitude and phase errors.

Using a simple trigonometric identity, the output of path Q can be broken down into sine and cosine parts.

In the absence of a mismatch between the I and Q paths (HΔ (ω) = 1), the ideal outputs of the quadrature sampling configuration can be defined as:

Therefore, for a sinusoidal or other narrowband signal centered at frequency ω0, the actual quadrature outputs can be written in terms of the ideal quadrature outputs. The direct quadrature setup can be viewed as a 2 × 2 linear system that generates a quadrature error. QEC is achieved by inverting this 2 × 2 linear system to recover the ideal outputs x_i (t) and x_q(t).

Figure 8. An expanded quadrature sampling model to show both the error terms and the error correction. The topology shown is a semicomplex filter and is consistent with the filter shown in Figure 4.

The analysis in Figure 8 describes the generation and correction of quadrature error when the system is stimulated at a single frequency. Since the 2 × 2 system is linear, the solution is easily generalized to broadband signals by introducing multitap FIR filters that vary their amplitude and phase responses as a function of frequency.

Quadrature Sampling with CFIR QEC:
The PFILT operates at the full sampling rate of 20 GSPS behind each ADC. The AD9084 also includes a complex FIR (CFIR) after decimation. The advantage of using this filter is that the correction can be applied for a longer period without increasing the number of filter taps. To achieve this, two complex DDCs (CDDCs) are used. The second CDDC shifts the image frequency to the negative image frequency within the primary DDC. By summing a weighted version of the complex conjugate of the second CDDC, image cancellation is created. The approach is shown in Figure 9.
Figure 9. Direct Quadrature Sampling with CFIR QEC.
The CFIR performs QEC in the same way as the PFILT. The only difference is that the correction is applied to the decimated output. To demonstrate this, the PFILT can be viewed as a network of complex filters, as opposed to the 2 × 2 linear system described earlier. The 2 × 2 linear system has the form shown below, where the inputs, outputs, and filter coefficients are all real-valued, and the symbol * indicates convolution.

If these real-value signals are combined and interpreted as complex-value signals, then the following properties are fulfilled.

Defining y[n] = yi [n] + jyq [n] and substituting using the properties given above, the complex value interpretation of the semicomplex PFILT structure can be derived.

The result is an alternative interpretation of the PFILT effect that implies:

1. Apply a complex-value linear filter b1[n] to the complex-value input y[n]. The b1[n] filter performs band equalization of Q compared to I to preserve the flatness of the desired signal.
2. Application of a complex-value linear filter b2[n] to the complex-value input y[n]. The b2[n] filter transforms the blocking signal into an anti-image that will destructively add to the unwanted image.
3. Add the output of the first filter to the complex conjugate of the output of the second filter. The time conjugation causes a frequency inversion that aligns the blocker and its frequency image, allowing a scaled and rotated version of the blocker to destructively summate with its image.

These are the exact steps that DDCs and CFIRs take to achieve QEC.

1. DDC1 converts the desired signal to lower frequencies, and CFIR1 applies a complex value linear filter with a response equivalent to b1n.
2. DDC2 converts the blocking signal to lower frequencies, and CFIR2 applies a complex value linear filter with a response equivalent to b2n.
3. The sum of the CFIR1 and CFIR2 outputs results in the rejection of the image.

Figure 10 shows examples of FFT measurements using the CFIR to achieve QEC.

Figure 10. Representative quadrature sampling FFT measurements using the CFIR for QEC. A blocker is injected at 13 GHz, creating an image at 7 GHz. The top graph is a full-rate capture of a 40 GSPS FFT before QEC. The bottom graphs are FFTs of decimated data, showing that the blocker image was reduced below 60 dBc.

Quadrature Error Training Approach:
The Quadrature Sampling with Programmable Filter section explains that discrepancies between the I and Q paths lead to quadrature errors. It also details how, if these mismatches were identified, the errors could be rectified using the semi-complex PFILT structure. The Quadrature Sampling with CFIR QEC section demonstrates that the same QEC can also be deferred to CFIRs at the DDC outputs. In both cases, the coefficients of the ideal correction filters depend on the mismatch response between the I and Q paths. This section describes one way to estimate the mismatch response.
There are multiple types of QEC algorithms. One way to differentiate between algorithms is based on the input stimulus used for training.
Online calibrations are performed while the system remains active, typically training on a timely basis using any input signal presented to the ADC. These calibrations can run in the background for extended periods and can adapt to changes in I/Q mismatch due to temperature, supply, and timing deviations.
Offline calibrations operate when the system is not active. Since the system is offline, known calibration signals can be introduced for training purposes. Once training is complete, the system can be brought back online, operating with fixed correction coefficients. Depending on the use case, the system might require periodic recalibration as system parameters deviate. The system must be taken offline again during recalibration.
The choice between online and offline calibration is application-specific, as both approaches have their advantages and disadvantages. The remainder of this discussion focuses on a form of offline calibration that injects a series of calibration tones into the system.
This calibration defines two bands of interest, as shown in Figure 11.
The desired band covers the desired output bandwidth of the system.
The blocking band is reflected across fs/2 relative to the desired band, where fs is the ADC sampling frequency. For example, if the desired band spans from frequency f1 to frequency f2, then the blocking band spans from fs - f2 to fs - f1. Large blocking signals appearing within the blocking band will generate a false image that falls within the desired band.
These two bands of interest can span any point between CC and fs/2 and can overlap.

Figure 11. QEC training involves sweeping frequencies both within the band of interest to ensure amplitude flatness and within the image band to ensure image rejection.

With regard to these two bands of interest, the QEC calibration has two objectives.

1. Reject images that fall within the desired band.
2. Preserve signals that fall within the desired band by matching the in-band gain and phase response of the Q path to the in-band gain and phase response of the I path. This is a form of relative equalization. The Q path is matched to the I path, but any drop-off within the I path is preserved.

These two objectives are related through the I/Q mismatch. As the Q path matches the I path, both in-band flatness and out-of-band image rejection improve simultaneously. Therefore, to achieve both objectives, calibration must learn the I/Q mismatch for both the desired and blocking bands, and then adjust the correction filter coefficients to perform relative Q-to-I equalization in both bands.
However, the two objectives do not necessarily have equal importance. In many applications, from an I/Q matching perspective, in-band flatness requirements can be met with relatively coarse I/Q matching, while image rejection objectives typically require much more precise I/Q matching.

Table 1 shows the in-band gain and phase errors corresponding to various image rejection levels. For example, if an application requires an in-band flatness of 1° and an image rejection of –50 dBc, the I/Q match needed to achieve the image rejection target is approximately five times more precise than that required for in-band flatness.

Table 1. Minimum errors required for image rejection performance

Table 2 shows an example training algorithm that applies unequal weighting for flatness compared to image rejection targets. Calibration tones are injected within the desired band so that flatness within that band can be improved. Calibration tones are also injected within the blocking band so that images falling within the desired band can be attenuated. When the desired band extends across fs/2, the desired band and the blocking band overlap. Calibration tones falling within the overlap region can be labeled as being within the blocking band, thus giving them a higher weighting factor to achieve the more challenging image rejection target.

Table 2. Training Algorithm

Measured Quadrature Sampling Image Rejection Results
Figure 12. Direct quadrature sampling image rejection measured from 2 GHz to 18 GHz. Both QEC, PFILT, and CFIR options are shown. The CFIR correction method shows results better than 50 dBc. The PFILT correction degrades slightly in this dataset and will be described in the following sections.
The measured image rejection results are shown in Figure 12. The results for both PFILT and CFIR corrections are shown. Using CFIR correction, image rejection of >50 dBc is achieved. The results using PFILT degrade slightly, and the root cause can be seen in the data shown in Figure 13. When evaluating the amplitude and phase mismatch before and after QEC, note that fairly serious errors are corrected, but a rapid ripple across the frequency remains after correction.
The PFILT operates at the full sampling rate, while the CFIR operates at a reduced and decimated sampling rate. Since the PFILT and CFIR have a similar number of taps, this means the CFIR can correct errors for a longer period than the PFILT. The end result is that the CFIR provides better correction for the test setup in use. However, ripple is currently limited by the impedance mismatch between the hybrid coupler and the ADC inputs, as well as the long transmission lines between them. Simulations show that ripple mismatch can be improved by mounting the hybrid coupler adjacent to the ADC inputs, which minimizes the small differences in signal path lengths.

Figure 13. Amplitude mismatch, phase mismatch, and image rejection before and after QEC when using PFILT QEC. Blue traces are before QEC. Purple traces are after QEC. PFILT correction is limited to 16 shots at maximum speed. With 16 shots, the correction is capable of correcting large errors that move slowly with frequency, but ripple that changes rapidly with frequency remains after correction. Ripple is limited by the test setup, where the impedance mismatch between the AD9084 and the quadrature hybrid is reflected through relatively long transmission lines. An integrated board solution will mount the quadrature hybrid directly next to the device.

Conclusion:
Direct quadrature sampling from 2 GHz to 18 GHz has been demonstrated. The following characteristics enabled this result:

1. A broadband quadrature hybrid
2. ADC with an inbound bandwidth through the second Nyquist zone
3. A method to ensure that ADC data is time-aligned
4. A FIR QEC filter at the ADC's maximum speed
5. A complex DDC to reduce data rates
6. A quadrature correction algorithm that resolves input imbalance errors within the reduced data rate DDC output bandwidth

The solution cannot be achieved using only one feature from this list. It is the combination of all these features that creates the solution. Without any of them, undesirable trade-offs might be necessary, or performance would be significantly reduced, rendering the solution unusable.
The approach presented provides a method for doubling the effective ADC sampling rate without doubling the digital data rates and while maintaining embedded DSP functionality. These benefits create a method for trading the number of channels versus the ADC frequency at the application level without ADC modifications. Direct quadrature sampling or quadrature interlacing does not replace time interlacing, but rather is an alternative to consider among many others as software-defined radio systems continue to mature.

References
1 Dave Frizelle and Frank Kearney. “Complex RF mixers, zero IF architecture and advanced algorithms: the black magic in next-generation SDR transceivers.” Analog Dialogue, vol. 17, February 2017.
2 Patrick Weirs. “Mirror, mirror on the wall: understanding image rejection and its impact on desired signals.” Analog Dialogue, vol. 51, August 2017.

About the authors:

Ian Beavers is a field applications engineer and customer lab manager for the Aerospace and Defense Systems team at Analog Devices in Durham, North Carolina. He has been with the company since 1999. Ian has over 25 years of experience in the semiconductor industry. He earned a bachelor's degree in electrical engineering from North Carolina State University and an MBA from the University of North Carolina at Greensboro.
Peter Delos is the technical lead for the Aerospace and Defense Group at Analog Devices in Greensboro, North Carolina. He earned his bachelor's degree in electrical engineering from Virginia Tech in 1990 and his MBA from NJIT in 2004. Peter has over 30 years of experience in the industry. He has dedicated most of his career to the design of advanced RF/analog systems at the architecture, PCB, and IC levels. Currently, he focuses on miniaturizing receiver designs, waveform generators, and high-performance synthesizers for phased-array applications.
Brian Reggiannini is a senior principal systems design engineer. He has designed, implemented, and supported system-level calibrations for several generations of Analog Devices wireless transceiver products. His technical interests include signal processing, machine learning, embedded systems, and systems involving digitally assisted analog components. Brian earned his Sc.B., Sc.M., and Ph.D. degrees from Brown University in 2007, 2009, and 2012, respectively.
Connor Bryant is a systems applications engineer at Analog Devices and works in the Aerospace and Defense Business Unit in Durham, North Carolina. He joined ADI in 2023. He currently focuses on the design and analysis of RF mixed-signal chains. He obtained his Bachelor of Science in Electrical Engineering from North Carolina State University in 2022 and his Master of Science in Electrical Engineering from North Carolina State University in 2023.

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