PAM4 technology enables future scaling of core/metro routers and hyperscale data centers up to 56 Gbps from 25 Gbps, in full duplex over differential pairs. Rack-level applications will particularly benefit from PAM4 technology, realizing the advantages in space, power, cost, and simplified cabling.
The Avago 56 Gbps PAM4 SerDes is designed to support a wide range of copper and optical interconnects, from chip-to-chip and chip-to-module to low-cost direct-attach cable and copper backboard, with losses as low as 35 dB. The SerDes supports speeds from 1 to 56 Gbps, including existing 10G/25G/40G/50G/100G Ethernet, Fibre Channel, and OIF IEC NRZ speeds, and provides investment protection and a focused path to network architecture for computer system vendors and massive data centers.
By also targeting the emerging electrical standards OIF CEI-56G-VSR and IEEE 802.3bs (400GE) that define the next generation of chip-to-module interconnects, Avago's SerDes 56 Gbps PAM4 provides the added benefit of enabling the same signaling deployment on the front and back side interfaces, thereby increasing SoC use case flexibility and reusability across hardware platforms.
Avago's 56 Gbps PAM4 SerDes, now available in silicon, flawlessly routes PRBS31 traffic across different interconnects up to 56 Gbps, thereby reducing ASIC development risk and accelerating Avago customer system deployment.
